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| trusted platform module tpm slb 9660 tcg rev. 116 slb 9660vq1.2 slb 9660tt1.2 slb 9660xt1.2 slb 9660xq1.2 chip card and security ics data sheet revision 1.0, 2014-12-12
data sheet 2 revision 1.0 2014-12-12 slb 9660 tpm1.2 trusted platform module revision history page or item subjects (major changes since previous revision) revision 1.0, 2014-12-12 initial version. slb 9660 tpm1.2 trusted platform module table of contents data sheet 3 revision 1.0 2014-12-12 table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 list of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 lpc interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 sync field usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 localities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.3 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.4 lpc access rights . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 device types / ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.1 typical schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.2 functional operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.3 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.4 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6 package dimensions (tssop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.1 packing type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.2 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.3 chip marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7 package dimensions (vqfn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.1 packing type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.2 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.3 chip marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table of contents slb 9660 tpm1.2 trusted platform module list of figures data sheet 4-4 revision 1.0 2014-12-12 figure 4-1 pinout of the slb 9660tt1.2 / slb 9660xt1.2 (pg-tss op-28-2 package, top view) . . . . . . . . . . . 8 figure 4-2 pinout of the slb 9660vq1.2 / slb 9660xq1.2 (pg-vqfn-32-13 package, top view) . . . . . . . . . . . 9 figure 4-3 typical schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 6-1 package dimensions pg-tssop-28-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 6-2 tape & reel dimensions pg-tssop-28-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 6-3 recommended footprint pg-tssop-28-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 6-4 chip marking pg-tssop-28-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 7-1 package dimensions pg-vqfn-32-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 7-2 tape & reel dimensions pg-vqfn-32-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 7-3 recommended footprint pg-vqfn-32-13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 7-4 chip marking pg-vqfn-32-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 list of figures slb 9660 tpm1.2 trusted platform module list of tables data sheet 5-5 revision 1.0 2014-12-12 table 2-1 lt register access matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 3-1 device configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 4-1 buffer types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 4-2 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 4-3 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 4-4 not connected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 5-1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 5-2 functional operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 5-3 current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 5-4 dc characteristics for non-lpc pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 5-5 dc characteristics for lpc pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 list of tables data sheet 6 revision 1.0 2014-12-12 slb 9660 tpm1.2 trusted platform module overview 1 overview the slb 9660 is a trusted platform modu le and is based on advanced hardwa re security technology. this tpm implementation has achieved cc eal4+ certification an d serves as a basis for ot her tpm 1.2 products and firmware upgrades. it is availa ble in different packages, see table 3-1 . it supports the lpc interface and interrupts are communicated with th e serial interrupt (serirq) protocol. features ? compliant to tpm main specif ication, version 1.2, rev. 116 ?lpc interface ? approved for google chromebook/chromebox ? standard (-20..+85c) and wide temperature range (-40..+85c) ? tssop-28 and vqfn-32 package ? optimized for battery operat ed devices: low standby po wer consumption (typ.150 a) ? 24 pcrs ? 6 kbytes free nv memory ? up to 10 concurrent sessions ? up to eight 2048-bit keys can be loaded into volatile storage ? 16 slots for keys of up to 2048-bit ? 8 monotonic counters ? 1280 bytes io buffer ? built-in support by linux? kernel version 3.10 and higher 2 lpc interface the slb 9660 features the low pin count (lpc) inte rface (for a specification, please refer to [1] ). from the cycle types defined in the mentioned specif ication, only the tpm-type cycles (read and write) are supported. all accesses with different cycle ty pes are ignored by the device. 2.1 sync field usage since the legacy interface is not su pported anymore, the slb 9660 will ne ver generate sync errors on the lpc. it will either acknowledge a cycle with sync ok or use a ?long wait? sync field to enlarge a cycle (that means, inserting wait states on the bus). 2.2 localities the interface explicitly does not su pport standard io cycles (read and write). this implies that io-mapped addressing of the device is not possible; only accesse s via the locality-based tp m-type cycles are possible which also means that ?loc ality none? as defined in [4] is not supported as well. for a detailed description of the locality addressing sc heme and the registers located in each locality, please refer to [4] as well. data sheet 7 revision 1.0 2014-12-12 slb 9660 tpm1.2 trusted platform module lpc interface 2.3 power management the slb 9660 does not support the lpc power down signal (signal lpcpd ) or the clock run protocol (signal clkrun ). power management is handled internally; no ex plicit power-down or standby mode is available. the device automatically enters a low-power state afte r each successful command/r esponse transaction. if a transaction is started on the lpc bus from the host pl atform, the device will wake immediately and will return to the low-power mode after the transaction has been finished. 2.4 lpc access rights the registers located in the addres s space of the slb 9660 are describe d in the respective tcg document (please refer to [4] ). the registers readfifo and writefifo mentioned in table 2-1 below refer to the datafifo register, the names are used to stat e whether this register is read or written. each register has its own access rights which describe if the register is updated on a write or can be read if the associated active.locality is set respec tively not set. if the access cycle is not accepted by the tpm, it will be master aborted (no lpc sync cycle will be generated and no action is done on the internal registers). table 2-1 shows which operation is done by the tpm on ea ch register depending on the active.locality bit. note: in table 2-1 , ?abort? means that no valid sync is generate d when a cycle is seen by the interface which shall be aborted. the data present in an aborted write access cycle does not change the addressed register. table 2-1 lt register access matrix active.locality set for this locality active.locality set for different locality active.locality not set read write read write read write sts read write abort abort abort abort int.enable read write read abort read abort int.vector read write read abort read abort int.status read reset interrupt read abort read abort int.capability read - (abort) read - (abort) read - (abort) access read write read write read write readfifo read 1) 1) if sts.data.avail is not set, this access is ?abort?. abort abort abort abort abort writefifo abort write abort abort abort abort configuration registers read write read abort read abort hash.start abort write abort abort abort write 2) 2) the write to hash.start sets ac cess.active.locality of locality 4. hash.data abort write abort abort abort abort hash.end abort write 3) 3) the write to hash.end is an implicit release of the tpm (like a ?1?-write to the access.active.locality bit of locality 4). abort abort abort abort data sheet 8 revision 1.0 2014-12-12 slb 9660 tpm1.2 trusted platform module device types / ordering information 3 device types / ordering information the slb 9660 product family features devices with different packages. table 3-1 shows the different versions. 4 pin description figure 4-1 pinout of the slb 9660tt1.2 / slb 9 660xt1.2 (pg-tssop-28-2 package, top view) table 3-1 device configuration device name package remarks slb 9660tt1.2 pg-tssop-28-2 standard temperature range slb 9660vq1.2 pg-vqfn-32-13 standard temperature range slb 9660xt1.2 pg-tssop-28-2 enh anced temperature range slb 9660xq1.2 pg-vqfn-32-13 en hanced temperature range nc nc nc gnd vdd gpio pp nc nc vdd gnd nc nc nc nc serirq la d0 gnd vdd la d1 lframe# lclk la d2 vdd gnd la d3 lrese t# nc tpm slb 9660tt1.2 pg-tssop-28-2 14 8 14 15 18 22 28 11 25 pinning_tssop-28-2_slb9660.vsd data sheet 9 revision 1.0 2014-12-12 slb 9660 tpm1.2 trusted platform module pin description figure 4-2 pinout of the slb 9660vq1.2 / slb 9660xq1.2 (pg-vqfn-32-13 package, top view) table 4-1 buffer types buffer type description ts tri-state pin st schmitt-trigger pin od open-drain pin table 4-2 i/o signals pin number name pin type buffer type function pg-tssop- 28-2 pg-vqfn- 32-13 26 27 lad0 i/o ts lpc address/data bit 0 multiplexed lpc command, address and data bus. connect these pins to the lad[3:0] pins of the lpc host. 23 24 lad1 i/o ts lpc address/data bit 1 see description of lad0 above. 20 21 lad2 i/o ts lpc address/data bit 2 see description of lad0 above. 17 19 lad3 i/o ts lpc address/data bit 3 see description of lad0 above. 22 23 lframe# i st lpc framing signal lpc framing signal. this pin is connected to the lpc lframe# signal and indicates the start of a new cycle on the lpc bus or the termination of a broken cycle. the signal is active low. vdd vdd nc nc nc nc nc gnd lad1 gnd pp nc nc serirq lad0 gnd vdd tpm slb 9660vq1.2 pg-vqfn-32-13 1 10 15 26 30 18 pinn in g_ vqfn-32-1 3_s lb 966 0. vsd lframe# lclk lad2 vdd lad3 lreset# nc 22 7 vdd gpio nc nc nc nc nc nc data sheet 10 revision 1.0 2014-12-12 slb 9660 tpm1.2 trusted platform module pin description 21 22 lclk i st clock input this pin provides the exte rnal clock for the chip and is typically connected to the pci clock of the host. the clock frequency range is 1 mhz - 33 mhz (nominal). 16 18 lreset# i st reset external reset signal. asserting this pin unconditionally resets the device. the signal is active low and is typically connected to the pcirst# signal of the host. 6 2 gpio i/o od general purpose i/o this pin is a general purpose i/o pin. it is defined as gpio-express-00, please refer to [4] and the pci-sig ecn ?trusted configuration space for pci express?. this pin may be left unconnected; however, to minimize power consumption, it shall be connected to a fixed level (either gnd or vdd) via an external resistor (4.7 k ..10 k ). 731ppist physical presence this pin should be connected to a jumper. the standard position of th e jumper should connect the pin to gnd. if the pin is connected to vdd, some special commands are enabled (for instance, the command tpm_forceclear, also refer to [3] ). this pin does not have an internal pull-up or pull- down resistor and must not be left floating. 27 28 serirq i/o ts serial interrupt request interrupt request signal, uses the serial interrupt request protocol (see [2] ). connect to the lpc host. table 4-2 i/o signals (continued) pin number name pin type buffer type function pg-tssop- 28-2 pg-vqfn- 32-13 data sheet 11 revision 1.0 2014-12-12 slb 9660 tpm1.2 trusted platform module pin description table 4-3 power supply pin number name pin type buffer type function pg-tssop- 28-2 pg-vqfn- 32-13 5, 10, 19, 24 1, 9, 10, 20, 25 vdd pwr ? power supply all vdd pins must be connected externally and should be bypassed to gnd via 100 nf capacitors. 4, 11, 18, 25 16, 26, 32 gnd gnd ? ground all gnd pins must be connected externally. table 4-4 not connected pin number name pin type buffer type function pg-tssop- 28-2 pg-vqfn- 32-13 1, 2, 3, 8, 12, 13, 14, 15, 28 3, 4, 5, 6, 7, 11, 12, 13, 14, 15, 17, 29, 30 nc nu ? not connected all pins must not be conn ected externally (must be left floating). 9 8 nc nu ? not connected this pin may be connected to the reset signal (for backward compatibility) or may be left floating. data sheet 12 revision 1.0 2014-12-12 slb 9660 tpm1.2 trusted platform module pin description 4.1 typical schematic figure 4-3 shows the typical schematic fo r the slb 9660. the power supply pi ns should be bypassed to gnd with capacitors located close to th e device. the physical presence input may be connected to a jumper as shown in the schematic; or it may be driven by other devices (this is application- or platform-dependent). figure 4-3 typical schematic slb 9660 lad[3:0] lclk lframe# lreset# serirq lclk serirq vdd gnd 3.3v 4x 100 nf (place close to device vdd/gnd pins) pp 3.3v j1 gpio nc gpio lframe# lreset# schematic _slb 9660 .vsd lad[3:0] 1 f data sheet 13 revision 1.0 2014-12-12 slb 9660 tpm1.2 trusted platform module electrical characteristics 5 electrical characteristics this chapter lists the maximum an d operating ranges for various electrical and timing parameters. 5.1 absolute maximum ratings attention: stresses above the max. values listed here may cause permanent damage to the device. exposure to absolute maximum rating conditio ns for extended period s may affect device reliability. maximum ratings are absolute rati ngs; exceeding only one of these values may cause irreversible damage to the integrated circuit. 5.2 functional operating range table 5-1 absolute maximum ratings parameter symbol values unit note or test condition min. typ. max. supply voltage v dd -0.3 ? 3.6 v ? voltage on any pin v max -0.3 ? v dd +0.3 v ? ambient temperature t a -20 ? 85 c standard temperature devices ambient temperature t a -40 ? 85 c enhanced temperature devices storage temperature t s -40 ? 125 c ? esd robustness hbm: 1.5 k , 100 pf v esd,hbm ? ? 2000 v according to eia/jesd22-a114-b esd robustness v esd,cdm ? ? 500 v according to esd association standard stm5.3.1 - 1999 latchup immunity i latch 100 ma according to eia/jesd78 table 5-2 functional operating range parameter symbol values unit note or test condition min. typ. max. supply voltage v dd 3.0 3.3 3.6 v ? ambient temperature t a -20 ? 85 c standard temperature devices ambient temperature t a -40 ? 85 c enhanced temperature devices useful lifetime 1) 1) the useful lifetime of the device is 5 (five) years with a duty cycle (that means, a power-on time) of 100%. an useful lifetime of 7 (seven) years can be guaranteed for a duty cycle of 70%. for both scenarios, it is assumed that the device will be used for calculations for approximately 5% of the maximum useful lifetime. ??5 y operating lifetime 1) ??5 y average t a over lifetime ? 55 ? c data sheet 14 revision 1.0 2014-12-12 slb 9660 tpm1.2 trusted platform module electrical characteristics 5.3 dc characteristics t a = 25c, v dd = 3.3v 0.3v unless otherwise noted note: current consumption does not include any currents flowing through resistive loads on output pins! for the definition of power/operating states , please refer to the acpi standard. note: device sleep mode will be entered after 30 se conds of inactivity after the last tpm command was executed. table 5-3 current consumption parameter symbol values unit note or test condition min. typ. max. current consumption in active mode i vdd_active 2.5 25 ma assuming operating state s0 , that means active. note that since the device is mostly in an internal sleep state in a ?typical? application, the typical average current consumption is far less than the maximum value. it is assumed that in a normal environment, the device is in an internal sleep state for approximately 90% of the operating time of the platform. current consumption in sleep mode i vdd_sleep 0.9 ma pins lreset#, lframe#, ladn, serirq = v dd . assuming operating state s0 with active clock. no ongoing internal tpm operation. the device is in an internal sleep state. current consumption in sleep mode with stopped clock i vdd_sleep_cs 150 a pins lreset#, lframe#, ladn, serirq = v dd and lclk = gnd. assuming operating state s3 with clock stopped. obviously, this value is zero if the tpm is not powered in s3 state (this is platform dependent). table 5-4 dc characteristics for non-lpc pins parameter symbol values unit note or test condition min. typ. max. input voltage high v ih 0.7 v dd v dd vgpio and pp pins input voltage low v il 00.3 v dd vgpio and pp pins input high leakage current i ih -15 15 a v in = v dd , gpio and pp pins data sheet 15 revision 1.0 2014-12-12 slb 9660 tpm1.2 trusted platform module electrical characteristics 5.4 timing some pads are disabled after deassertion of the reset signal for up to 500 s. this is especially important for the serirq signal; after deassertion of the reset signal, this signal is on ly valid after that time has expired. input low leakage current i il -15 15 a v in = 0v, gpio and pp pins output high voltage v oh v dd -0.3 v i oh = 1ma, pin gpio output low voltage v ol 0.3 v i ol = 1ma, pin gpio table 5-5 dc characteristics for lpc pins parameter symbol values unit note or test condition min. typ. max. nput voltage high v ih 0.5 v dd v dd +0.3 v all signal pins except gpio and pp input voltage low v il -0.3 0.28 v dd v all signal pins except gpio and pp input high leakage current i ih -10 10 a v in = v dd , all signal pins except gpio and pp input low leakage current i il -10 10 a v in = 0v, all signal pins except gpio and pp output high voltage v oh 0.9 v dd vi oh = -500a, pins lad[3:0] and serirq output low voltage v ol 0.1 v dd vi ol = 1.5ma, pins lad[3:0] and serirq table 5-4 dc characteristics for non-lpc pins (continued) parameter symbol values unit note or test condition min. typ. max. data sheet 16 revision 1.0 2014-12-12 slb 9660 tpm1.2 trusted platform module package dimensions (tssop) 6 package dimensions (tssop) all dimensions are given in millimeters (mm) unless otherwise noted. the pack ages are ?green? and rohs compliant. figure 6-1 package dimensions pg-tssop-28-2 6.1 packing type pg-tssop-28-2: tape & reel (ree l diameter 330mm), 3000 pcs. per reel figure 6-2 tape & reel dimensions pg-tssop-28-2 0.1 m abc 28x 1.1 max. stand off c c 0.1 28x 0.65 0.22 +0.08 -0.03 2) 13 x 0.65 = 8.45 coplanarity seating plane 0.1 0.05 0.9 0.05 1 28 14 15 9.7 0.1 a 1) index marking b 0.1 3) 4.4 0.127 +0 .073 -0.03 7 0... 8 6.4 0.1 0.6 pg-tssop-28-2, -16-po v07 1) does not include plastic or metal protrusion of 0.15 max. per side 2) does not include dambar protrusion of 0.08 max. per side 3) does not include interlead flash or protrusion of 0.25 max. per side 2x 14 tips 0.2 c a-b, h h 10.2 16 1. 6 1. 2 8 0.3 6.8 pg-tssop-28-2, -16-tp v0 1 i ndex m arking data sheet 17 revision 1.0 2014-12-12 slb 9660 tpm1.2 trusted platform module package dimensions (tssop) 6.2 recommended footprint figure 6-3 recommended footprint pg-tssop-28-2 6.3 chip marking line 1: slb9660tt12 or slb9660xt12, see table 3-1 line 2: g data sheet 18 revision 1.0 2014-12-12 slb 9660 tpm1.2 trusted platform module package dimensions (vqfn) 7 package dimensions (vqfn) all dimensions are given in millimeters (mm) unless otherwise noted. the pack ages are ?green? and rohs compliant. figure 7-1 package dimensions pg-vqfn-32-13 7.1 packing type pg-vqfn-32-13: tape & reel (reel diameter 330mm), 5000 pcs. per reel figure 7-2 tape & reel dimensions pg-vqfn-32-13 7.2 recommended footprint figure 7-3 shows the recommended footpr int for the pg-vqfn-32-13 pack age. the exposed pad of the package is internally connected to gnd. it shall be connect to gn d externally as well. figure 7-3 recommended footprint pg-vqfn-32-13 32x 0.9 max. (0.2) seating plane c 0.05 max. 0.05 c 0.1 c 7 x 0.5 = 3.5 0.5 0.4 0.05 (4.2) 0.1 32x b m ac 0.05 m c -0.07 +0.05 0.25 81 32 25 24 17 9 16 0.1 3.6 0.1 3.6 index marking b index marking a 5 5 0.1 a 2x 0.1 b 2x pg-vqfn-32-13-po v01 12 5.25 5.25 8 0.3 1.1 index marking pg-vqfn-32-13-tp v01 pg-vqfn-32-13-fp v01 package outline 5 x 5 3.6 3.6 4.1 4.1 0.5 0.25 0.7 data sheet 19 revision 1.0 2014-12-12 slb 9660 tpm1.2 trusted platform module package dimensions (vqfn) 7.3 chip marking line 1: slb 9660 line 2: vq12 yy or xq12 yy (see table 3-1 ), the data sheet 20 revision 1.0 2014-12-12 slb 9660 tpm1.2 trusted platform module references references [1] ?, ?low pin count (lpc) interface specification?, version 1.1, intel [2] ?, ?serialized irq support for pci systems?, vers ion 6.0, september 1, 1995, cirrus logic et al. [3] ?, ?tpm main specificat ion?, version 1.2, rev. 116, 2011-03-01, tcg (parts 1-3) [4] ?, ?tcg pc client tpm interface specif ication (tis)?, versio n 1.3, 2013-03-21, tcg data sheet 21 revision 1.0 2014-12-12 slb 9660 tpm1.2 trusted platform module terminology terminology esw embedded software hmac hashed message authentication code lpc low pin count (bus) pcr platform configuration register pubek public endorsement key scp symmetric crypto processor tcg trusted computing group tpm trusted platform module tss tcg software stack trademarks of infineon technologies ag aurix?, c166?, canpak?, cipos?, coolgan?, coolmos?, coolset?, cool sic?, corecontrol?, crossave?, dave?, di-pol?, drblade?, easy pim?, econobridge?, econodual?, econopack?, econop im?, eicedriver?, eupec?, fcos?, hitfet?, hybridpack?, isofac e?, isopack?, mipaq?, modstack?, my-d?, novalithic?, omnitune?, optiga?, optimos?, origa?, po wercode?, primarion?, primepac k?, primestack?, profet?, pro- sil?, rasic?, real3?, reversave?, satric?, sieget?, sipmos?, smar tlewis?, solid flash?, spoc?, te mpfet?, thinq!?, trenchstop?, tricore?. other trademarks vision?, amba?, arm?, keil?, multi-ice?, th umb? of arm limited, uk. autosar? of auto sar development partnership. cipurse? of o spt alliance. emv? of emvco, llc (visa holdings inc.). flexgo? of microsoft co rporation. hypertermina l? of hilgraeve incorporated. irda? of i nfrared data association corporation. mcs? of intel corp. microwave office? (mwo) of applied wave research inc. teaklite? of ceva, inc. vxwo rks? of wind river systems, inc. chrome os? of google, inc. trademarks update 2014-07-17 edition 2014-12-12 published by infineon technologies ag 81726 munich, germany ? 2014 infineon technologies ag. all rights reserved. do you have a question about any aspect of this document? email: erratum@infineon.com document reference legal disclaimer the information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, infineon technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non- infringement of intellectual property rights of any third party. information for further information on technology, delivery terms and conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contain dangerous substances. for information on the types in question, please contact the nearest infineon technologies office. infineon technologies components may be used in life-support devices or systems only with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered. www.infineon.com |
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